1. Field of the Invention
The present invention relates generally to management of the initial communication between a pair of stations in a data transmission network, prior to the insertion of a new station into the data transmission ring. More particularly, a state machine user interface is provided that permits the user to control the connection management sequence.
2. Discussion of the Prior Art
One type of high speed data transmission network is defined by the Fiber Distributed Data Interface (FDDI) protocol. The FDDI protocol is an American National Standards Institute (ANSI) data transmission standard which applies to a 100 Mbit/second token ring network that utilizes an optical fiber transmission medium. The FDDI protocol is intended as a high performance interconnection between a number of computers as well as between the computers and their associated mass storage subsystem(s) and other peripheral equipment.
Information is transmitted on an FDDI ring in frames that consist of 5-bit characters or "symbols", each symbol representing 4 data bits. Information is typically transmitted in symbol pairs or "bytes". Tokens are used to signify the right to transmit data between stations. The FDDI standard includes a thirty-two member symbol set. Within the set, sixteen symbols are data symbols (each representing 4 bits of ordinary data) and eight are control symbols. The eight control symbols are: J (the first symbol of a start delimiter byte JK), K (the second symbol of a start delimiter byte JK), I (Idle), H (Halt), Q (Quiet), T (End Delimiter), S (Set) and R (Reset). The remaining eight symbols of the FDDI standard symbols set are not used since they violate code run length and DC balance requirements of the protocol. These are referred to as V (violation) symbols.
In operation, a continuous stream of control symbol patterns defines a "line stat". The FDDI protocol defines several line states, which include the following line states that are used during the connection management sequence:
(1) Idle Line State (ILS), which is a continuous stream of Idle symbols; PA0 (2) Quiet Line Sate (QLS), which is a continuous stream of Quiet symbols; PA0 (3) Halt Line State (HLS), which is a continuous stream of Halt symbols; PA0 (4) Master Line State (MLS), which is an alternating stream of Halt and Quiet symbols; and PA0 (5) Active Line State (ALS), which is the state used to transmit data units (frames)
The FDDI Station Management (SMT) standard provides the necessary control of an FDDI station (node) so that the node may work cooperatively as a part of an FDDI network. To effectively implement the functions required, SMT is divided into three entities, namely the Connection Management entity (CMT), the Ring Management entity (RMT) and the Frame Based Services. The Connection Management (CMT) is the management entity in the Station Management that is responsible for the station's port(s), as well as the connection to the ports of neighboring stations.
The Connection Management is further divided into three sub-entities. They include, the Physical Connection Management (PCM), Configuration Management (CFM) and Entity Coordination Management (ECM).
The introduction of an FDDI station (node) into the data flow path of the FDDI ring is governed by the Physical Connection Management (PCM) entity. One of the most important functions of Physical Connection Management (PCM) is to establish a connection between two ports that are directly connected. The connection process is achieved through a lock-step handshaking procedure. In the basic FDDI sequence, the handshaking procedure controlled by the PCM is divided into three stages. They include an initialization sequence, a signaling sequence and a join sequence. The initialization sequence is used to indicate the beginning of the PCM handshaking process. It forces the neighboring PCM into a known state so that the two PCM state machines can run in a lock-step fashion.
Following the initialization sequence is the signaling sequence. The signaling sequence communicates basic information about the port and the node with the neighboring port. A Link Confidence Test (LCT) is also conducted during the signaling sequence to test the link quality between the two ports. If the link quality is not acceptable or the type of connection is not supported or is currently not accepted by the nodes then the connection will be withheld. If the connection is not withheld during the signaling sequence, the PCM state machine can move on to the join sequence and establish a connection between the two neighboring ports.
In order to manage the initial connection between the ports of separate stations, the PCM manages the physical layer, controls the line-states transmitted during initiation and monitors the line-states received during the connection initialization. The PCM block itself is generically subdivided into two entities. The PCM State Machine and the Pseudo Code. The PCM State Machine contains all the state and timing information of the PCM and provides a signalling channel. The Pseudo Code specifies the bits that are to be signalled by the PCM State Machine and processes the bits received from the PCM at the other end of the link.
A general description of the Station Management standard, as well as each of its subparts, including the PCM is described in detail in the draft ANSI FDDI Station Management Standard, dated Jun. 25, 1992, which is incorporated herein by reference.
The basic FDDI protocol has a defined connection management sequence for making a duplex connection between a pair of stations. As seen in FIG. 1, the PCM State Machine is likely to enter a total of seven states during the connection sequence. These include the following states: PC1:Break; PC3:Connect; PC4:Next; PC5:Signal; PC6:Join; PC7:Verify; and PC8:Active. There are three other states that the PCM is generally capable of entering as well. That is, PC0:Off, PC2:Trace and PC9:Maint. The PC0:Off state occurs when the port is shut down. PC2:Trace relates to locating faults in the token ring. PC9:Maint relates to maintenance functions.
The Off state (PC0) is the initial state of the PCM State Machine. The PCM returns to this state upon the reception of a PC.sub.-- Stop signal. In the Off state, the Physical Layer (PHY) device transmits Quiet symbols and the optical transmitter may be disabled. The Break State (PC1) is the beginning of the PCM connection sequence. The Break state is entered upon the reception of the PC.sub.-- Start signal. The Break state is also entered from any other state when the connection sequence cannot be completed and a reinitialization is required for any reason.
The Connect state (PC3) is used to synchronize two ports to establish an initial contact and to begin the signaling sequence. In the Connect state, the optical transmitter is enabled and a continuous stream of Halt symbols is transmitted. When a Halt line state is received from the adjacent node, the state machine leaves the Connect state and enters the Next state (PC4). On the other hand, if an Idle line state is received before a Halt line state, then the connection is not synchronized and the state machine transits to the Break state to restart the connection sequence.
The Next state (PC4) is one of the two states used in the signaling sequence. The main purpose of the Next state is to separate the "bit" signaling performed in the Signal state (PC5). The Next state is also used to transmit Protocol Data Units (PDUs) while a loop test such as a Link Confidence Test or optionally, a Media Access Control Layer (MAC) Local Loop Test is performed. The PCM Pseudo Code machine is also started in the Next State. On initial entry into the Next state, a continuous stream of Idle symbols is transmitted. While in the Next state, either a continuous stream of Idle symbols or a PDU symbol stream is transmitted.
The Next state terminates and the state machine transits to the Signal state (PC5) upon the reception of either a Halt or a Master line states after a loop test. The same transition is made when a PC.sub.-- Signal signal is received from the Pseudo Code machine. When a PC.sub.-- Join signal is received, a transition is made to the Join state. If for any reason a Quiet line state is received while the state machine is in the Next state, the state machine transits to the Break state to permit a restart.
The Signal state is the second state used in the signaling sequence. In the Signal state, individual bits of information are communicated between ports by transmitting either Halt symbols or Master symbol pairs. The transmission of a Halt line state is equated with a logical one, and the transmission of the Master line state is a logical zero. Once each individual bit has been transmitted and received, the state machine returns to the Next state (i.e. the transmission of the Idle line state), before returning to the Signal state to transmit the next bit of information. Thus, the Next state is used as a bit delimiter between two signaling bits. When all signal bits have been transmitted and received, the Signaling sequence ends.
The Join state (PC6) is the first of three states in the join sequence that leads to an active connection. The join sequence assures that both ends of a connection enter the Active state together at the completion of the sequence. The Join state is entered upon the completion of the signal sequence when the PC.sub.-- Join signal is issued from the Pseudo Code machine. In the Join state, a continuous stream of Halt symbols is transmitted.
The Verify state (PC7) is the second of the three join sequence states. The Verify state is entered when the Halt line state is received from the adjacent node. In the Verify state, the PCM transmits a Master line state. The Join and Verify states combine to produce a sequence of line states, the halt line state followed by the master line state, which is unique in the connection management sequence.
The Active state (PC8) is the last of the three states in the join sequence. In this state, a continuous stream of Idle symbols is transmitted. Upon the reception of an Idle line state from the adjoining node, the physical layer device is allowed to enter the Active Transmit Mode and thus becomes part of the active ring. In addition to the normal break conditions, if a Halt line state is received in place of the Idle line state, the connection is not synchronized and a reinitialization of the connection is required. Similarly, if the Link Error Rate is too high, the connection must be reinitialized.
The basic FDDI protocol (referred to as FDDI-1) has a defined connection management sequence as seen in FIG. 2b. The ANSI standards committee is currently working on an enhanced version of FDDI, which is generally referred to as the FDDI-II standard. At the time of this writing, the connection management sequence for FDDI-II had not been finalized. However, there are several proposed connection management sequences for FDDI-II. One such proposed sequence for a duplex connection is shown in FIG. 2c. As seen therein, it is expected that the sequence will be generally similar schematically to the protocol for a FDDI-I connection. Similarly, the state machine for a FDDI-II duplex connection is expected to be essentially the same as the state machine for a basic FDDI-1 connection. However, the information carried in the various pseudo code bits is expected to be somewhat different.
Although the FDDI protocol is based primarily on the concept of a dual ring wherein communications are possible between nodes in both directions (i.e. a duplex connection), some parties have proposed that the FDDI-II standards facilitate the use of simplex connections as well. Simplex connections are intended to connect single-attached stations. The intent of the simplex connection scheme is to permit the transmission of ring information through stations on a side lobe. Within the side lobe, communication would be possible in only one direction. Thus, when the lobe is in operation, all information within the ring would pass directly through each station on the side lobe.
Since the handshaking procedure discussed above for a duplex connection is not possible in a simplex connection, the connection management sequence for a simplex connection is necessarily much simpler than that required for a duplex connection. A proposed simplex connection sequence is shown in FIG. 2a, while FIG. 1 shows the required PCM states for both simplex and duplex connections. As seen therein, the Connect, Next, Signal, and Join states are all skipped entirely in the simplex connection.
Since FDDI standards have not yet been finalized, and indeed are likely to be subject to change for some time, it is desirable for system designers to have a single chip set that can not only accommodate each of these different connection management sequences, but also remains adaptable to accommodate emerging FDDI standards and specialized user requirements.